Accompanied with continual development of electronic technology, various electronic products are becoming more and more compact and versatile with overwhelmingly diversified functions. Therefore, a large number of electronic devices of all types need be provided in a chip having a relatively small area in order to meet actual requirements of the electronic products.
However, in certain circuit layouts, it happens that the number of electronic devices within a given area becomes too large. That is, a density of the electronic devices in the area is too high, such that routing between the electronic devices within the area becomes infeasible. The circuit layout may not only fail to pass design rule checking, but the circuit itself may be unable to function normally.
FIG. 1 shows a conventional logic circuit layout in a gate level HDL. For example, a logic circuit layout 1 comprises a plurality of devices, with a large logic cone formed as a synthesized result from synthesis.
In order to enable the logic circuit layout 1 to pass time constraints as well as reducing a utilization area thereof, all electronic devices in the logic circuit layout 1 are coupled to or merged with one another, or simplified. Consequently, complex connections are developed between a synthesized logic circuit layout, thus forming the large logic cone shown in FIG. 1.
The logic circuit layout 1, after the synthesis procedure, undergoes automatic placement-and-routing (APR) to form the logic circuit layout 1 comprising combinational logic devices c (e.g., NAND and OR logic gates) and sequential logic devices s (e.g., flip-flops), as shown in FIG. 2. With reference to FIG. 2, it is observed that, quite a number of combinational logic devices c are crowded at a congestive area 20 resulting in heavy congestion due to a high density of the combinational logic devices c. Such high density of electronic devices adds complications to routings between the electronic devices whereby the logic circuit layout 1 may fail to pass design rule checking.
Therefore, it is an objective of the invention to provide a method and apparatus for preventing congestive placement in circuit layout.